Exemplary embodiments relate generally to an integrated circuit and, more particularly, to a semiconductor memory device and a method of erasing the same.
The memory array of a memory device, e.g., a flash memory device such as a NAND flash memory device includes a plurality of memory blocks. Each of the memory blocks includes a plurality of strings. Each of the strings includes a source select transistor coupled to a common source line, a plurality of memory cells, and a drain select transistor coupled to a bit line.
Prior to a program operation for storing data in specific memory cells of the flash memory device, an erase operation for erasing data stored in the specific memory cells must be performed. In the case of the NAND flash memory, the erase operation is performed on a memory-block basis. Therefore, each memory-block is a unit of erase operation, and even if only a portion of the memory-block is updated, all the cells included in a corresponding memory-block is erased and then programmed, and thus this increases the time taken to update data in the specific memory cells.